1. Field of the Invention
This invention relates to an Input/Output selection circuit for column repair, and more particularly, relates to an Input/Output selection circuit for column repair, in which only a few fuses are blown for selecting an Input/Output from a plurality of Input/Output from a plurality of Input/Outputs.
2. Description of the Prior Art
Generally, in a memory device operating a plurality of Input/Output using one address (e.g., byte wide), the failed Input/Output should be selected among a plurality of Input-out with one number of spare columns. If an Input/Output selection circuit is not employed, the spare column should be required in proportion to the number of Input/Output, thus enlarging the layout area.
A prior art Input/Output selection circuit of column repair, as illustrated in FIG. 1, has the following structure:
An input of two spare bits of SB and SB is commonly given to the drain; the source of n pair of NMOS transistor NM11, NM12; NM21; NM22; . . . NMn1, NMn2 is respectively connected with each of data bus DB1;-DB.sup.n, DBn; the respective gates of these transistor pairs are connected to ground through the resistor R1-Rn, while the connection point between the gates of each transistor pair is given ready signal, O REDY through inverter I1 after passing n-piece of fuse F1-Fn. Thus, in accordance with this prior art, Input/Output selection part, selecting the failed Input/Output among n-piece of Input/Output is equally fabricated with n-piece.
As for the technical operation of prior art as fabricated above, if the repaired address is selected, a ready signal O REDY is in the low level whereas if the repaired address is not selected, a ready signal O REDY is in the high level.
Since the bit line SB, SB of one more spare column is applied to the drain terminal (i.e. for each Input/Output) of n pair of NMOS transistors NM11; . . . NMn1, NMn2 or if, for example, `I/O 1` from n-piece of Input/Output I/O 1 to I/O n is failed, the remaining fuse from F1 to Fn excluding fuse F1, that is, n-1 piece of fuse, should be blown, as the remaining Input/Output fuse excluding the failed Input/Output from n-piece of fuse F1 to Fn should be blown.
Not that the fuse F-2 are blown, the gate voltage of NMOS transistors NM11, NM12; NM21, NM22; . . . NMn2, NMn2 is in the low level by the grounded resistors R2-Rn so that the line information of spare bit line SB, SB is not delivered to data bus DB2, DB2; . . . DBn, DBn.
Meantime, in case that the Input/Output I/O 1 is repaired, the gate node point of NMOS transistor NM11, NM12 is controlled by ready signal O REDY because the fuse F1 is not blown. Among the failed Input/Output, therefore, only the 1st Input/Output I/O 1 is controlled by a ready signal O REDY and thus, only Input/Output I/O 1 is repaired. Since the said conventional Input/Output selection circuit of column repair has to blow n-1 piece of fuse per spare column all the time, however, a lot of space columns should be necessary in the high integrated memory device, thus generating an excessive number of fuse blowing.